//                                                                             
// File:       ./chn1_table_map.vrh                                            
// Creator:    tyzhang                                                         
// Time:       Monday Sep 24, 2012 [8:14:05 pm]                                
//                                                                             
// Path:       /trees/mbu-cn1/tyzhang/tianfang_enc_depot/chips/rome/dev/doc/headers/wl_soc_mac
// Arguments:  /cad/denali/blueprint/3.7.4//Linux-64bit/blueprint -odir .      
//             -codegen ath_vrh.codegen -ath_vrh -Wdesc ./chn1_table_map.rdl   
//                                                                             
// Sources:    /trees/mbu-cn1/tyzhang/tianfang_enc_depot/chips/rome/dev/doc/ip/R1_IP5/rtl/bb_2x2/blueprint/chn1_table_map.rdl
//             /trees/mbu-cn1/tyzhang/tianfang_enc_depot/chips/rome/dev/env/blueprint/ath_vrh.pm
//             /cad/local/lib/perl/Pinfo.pm                                    
//                                                                             
// Blueprint:   3.7.4 (Fri Jan 9 05:41:17 PST 2009)                            
// Machine:    apr11                                                           
// OS:         Linux 2.6.9-89.ELsmp                                            
// Description:                                                                
//                                                                             
// No Description Provided                                                     
//                                                                             
//                                                                             


#ifndef _CHN1_TABLE_MAP_H_
#define _CHN1_TABLE_MAP_H_
// 0x0080 (BB_PAPRD_POWER_AT_AM2AM_CAL_B1)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_MSB 29
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_LSB 24
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_MASK 0x3f000000
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_GET(x) (((x) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_MASK) >> BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_LSB)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_SET(x) (((0 | (x)) << BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_LSB) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_MASK)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_RESET 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_MSB 23
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_LSB 18
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_MASK 0x00fc0000
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_GET(x) (((x) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_MASK) >> BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_LSB)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_SET(x) (((0 | (x)) << BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_LSB) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_MASK)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_RESET 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_MSB 17
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_LSB 12
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_MASK 0x0003f000
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_GET(x) (((x) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_MASK) >> BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_LSB)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_SET(x) (((0 | (x)) << BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_LSB) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_MASK)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_RESET 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_MSB 11
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_LSB 6
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_MASK 0x00000fc0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_GET(x) (((x) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_MASK) >> BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_LSB)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_SET(x) (((0 | (x)) << BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_LSB) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_MASK)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_RESET 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_0_B1_MSB 5
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_0_B1_LSB 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_0_B1_MASK 0x0000003f
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_0_B1_GET(x) (((x) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_0_B1_MASK) >> BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_0_B1_LSB)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_0_B1_SET(x) (((0 | (x)) << BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_0_B1_LSB) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_0_B1_MASK)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_0_B1_RESET 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_ADDRESS                       0x0080
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_HW_MASK                       0x3fffffff
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_SW_MASK                       0x3fffffff
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_HW_WRITE_MASK                 0x00000000
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_SW_WRITE_MASK                 0x3fffffff
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_RSTMASK                       0xc0000000
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_RESET                         0x00000000

// 0x0084 (BB_PAPRD_VALID_OBDB_B1)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_MSB             29
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_LSB             24
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_MASK            0x3f000000
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_GET(x)          (((x) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_MASK) >> BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_LSB)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_SET(x)          (((0 | (x)) << BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_LSB) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_MASK)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_RESET           63
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_MSB             23
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_LSB             18
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_MASK            0x00fc0000
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_GET(x)          (((x) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_MASK) >> BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_LSB)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_SET(x)          (((0 | (x)) << BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_LSB) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_MASK)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_RESET           63
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_MSB             17
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_LSB             12
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_MASK            0x0003f000
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_GET(x)          (((x) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_MASK) >> BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_LSB)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_SET(x)          (((0 | (x)) << BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_LSB) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_MASK)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_RESET           63
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_MSB             11
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_LSB             6
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_MASK            0x00000fc0
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_GET(x)          (((x) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_MASK) >> BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_LSB)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_SET(x)          (((0 | (x)) << BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_LSB) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_MASK)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_RESET           63
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_MSB             5
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_LSB             0
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_MASK            0x0000003f
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_GET(x)          (((x) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_MASK) >> BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_LSB)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_SET(x)          (((0 | (x)) << BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_LSB) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_MASK)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_RESET           63
#define BB_PAPRD_VALID_OBDB_B1_ADDRESS                               0x0084
#define BB_PAPRD_VALID_OBDB_B1_HW_MASK                               0x3fffffff
#define BB_PAPRD_VALID_OBDB_B1_SW_MASK                               0x3fffffff
#define BB_PAPRD_VALID_OBDB_B1_HW_WRITE_MASK                         0x00000000
#define BB_PAPRD_VALID_OBDB_B1_SW_WRITE_MASK                         0x3fffffff
#define BB_PAPRD_VALID_OBDB_B1_RSTMASK                               0xffffffff
#define BB_PAPRD_VALID_OBDB_B1_RESET                                 0x3fffffff

// 0x0100 (BB_CHN1_TABLES_DUMMY_2)
#define BB_CHN1_TABLES_DUMMY_2_DUMMY2_MSB                            31
#define BB_CHN1_TABLES_DUMMY_2_DUMMY2_LSB                            0
#define BB_CHN1_TABLES_DUMMY_2_DUMMY2_MASK                           0xffffffff
#define BB_CHN1_TABLES_DUMMY_2_DUMMY2_GET(x)                         (((x) & BB_CHN1_TABLES_DUMMY_2_DUMMY2_MASK) >> BB_CHN1_TABLES_DUMMY_2_DUMMY2_LSB)
#define BB_CHN1_TABLES_DUMMY_2_DUMMY2_SET(x)                         (((0 | (x)) << BB_CHN1_TABLES_DUMMY_2_DUMMY2_LSB) & BB_CHN1_TABLES_DUMMY_2_DUMMY2_MASK)
#define BB_CHN1_TABLES_DUMMY_2_DUMMY2_RESET                          0
#define BB_CHN1_TABLES_DUMMY_2_ADDRESS                               0x0100
#define BB_CHN1_TABLES_DUMMY_2_HW_MASK                               0xffffffff
#define BB_CHN1_TABLES_DUMMY_2_SW_MASK                               0xffffffff
#define BB_CHN1_TABLES_DUMMY_2_HW_WRITE_MASK                         0x00000000
#define BB_CHN1_TABLES_DUMMY_2_SW_WRITE_MASK                         0xffffffff
#define BB_CHN1_TABLES_DUMMY_2_RSTMASK                               0x00000000
#define BB_CHN1_TABLES_DUMMY_2_RESET                                 0x00000000

// 0x0890 (BB_TXIQCORR_TXPATH_COEF_B1_0)
#define BB_TXIQCORR_TXPATH_COEF_B1_0_TXIQCORR_TXPATH_COEF_CHN1_MSB   17
#define BB_TXIQCORR_TXPATH_COEF_B1_0_TXIQCORR_TXPATH_COEF_CHN1_LSB   0
#define BB_TXIQCORR_TXPATH_COEF_B1_0_TXIQCORR_TXPATH_COEF_CHN1_MASK  0x0003ffff
#define BB_TXIQCORR_TXPATH_COEF_B1_0_TXIQCORR_TXPATH_COEF_CHN1_GET(x) (((x) & BB_TXIQCORR_TXPATH_COEF_B1_0_TXIQCORR_TXPATH_COEF_CHN1_MASK) >> BB_TXIQCORR_TXPATH_COEF_B1_0_TXIQCORR_TXPATH_COEF_CHN1_LSB)
#define BB_TXIQCORR_TXPATH_COEF_B1_0_TXIQCORR_TXPATH_COEF_CHN1_SET(x) (((0 | (x)) << BB_TXIQCORR_TXPATH_COEF_B1_0_TXIQCORR_TXPATH_COEF_CHN1_LSB) & BB_TXIQCORR_TXPATH_COEF_B1_0_TXIQCORR_TXPATH_COEF_CHN1_MASK)
#define BB_TXIQCORR_TXPATH_COEF_B1_0_TXIQCORR_TXPATH_COEF_CHN1_RESET 0
#define BB_TXIQCORR_TXPATH_COEF_B1_0_ADDRESS                         0x0890
#define BB_TXIQCORR_TXPATH_COEF_B1_ADDRESS                           BB_TXIQCORR_TXPATH_COEF_B1_0_ADDRESS
#define BB_TXIQCORR_TXPATH_COEF_B1_0_HW_MASK                         0x0003ffff
#define BB_TXIQCORR_TXPATH_COEF_B1_0_SW_MASK                         0x0003ffff
#define BB_TXIQCORR_TXPATH_COEF_B1_0_HW_WRITE_MASK                   0x00000000
#define BB_TXIQCORR_TXPATH_COEF_B1_0_SW_WRITE_MASK                   0x0003ffff
#define BB_TXIQCORR_TXPATH_COEF_B1_0_RSTMASK                         0xffffffff
#define BB_TXIQCORR_TXPATH_COEF_B1_0_RESET                           0x00000000

// Skip 894 (BB_TXIQCORR_TXPATH_COEF_B1_1) - 8cc (BB_TXIQCORR_TXPATH_COEF_B1_15) for brevity
// 0x08d0 (BB_TXIQCORR_RXPATH_COEF_B1_0)
#define BB_TXIQCORR_RXPATH_COEF_B1_0_TXIQCORR_RXPATH_COEF_CHN1_MSB   17
#define BB_TXIQCORR_RXPATH_COEF_B1_0_TXIQCORR_RXPATH_COEF_CHN1_LSB   0
#define BB_TXIQCORR_RXPATH_COEF_B1_0_TXIQCORR_RXPATH_COEF_CHN1_MASK  0x0003ffff
#define BB_TXIQCORR_RXPATH_COEF_B1_0_TXIQCORR_RXPATH_COEF_CHN1_GET(x) (((x) & BB_TXIQCORR_RXPATH_COEF_B1_0_TXIQCORR_RXPATH_COEF_CHN1_MASK) >> BB_TXIQCORR_RXPATH_COEF_B1_0_TXIQCORR_RXPATH_COEF_CHN1_LSB)
#define BB_TXIQCORR_RXPATH_COEF_B1_0_TXIQCORR_RXPATH_COEF_CHN1_SET(x) (((0 | (x)) << BB_TXIQCORR_RXPATH_COEF_B1_0_TXIQCORR_RXPATH_COEF_CHN1_LSB) & BB_TXIQCORR_RXPATH_COEF_B1_0_TXIQCORR_RXPATH_COEF_CHN1_MASK)
#define BB_TXIQCORR_RXPATH_COEF_B1_0_TXIQCORR_RXPATH_COEF_CHN1_RESET 0
#define BB_TXIQCORR_RXPATH_COEF_B1_0_ADDRESS                         0x08d0
#define BB_TXIQCORR_RXPATH_COEF_B1_ADDRESS                           BB_TXIQCORR_RXPATH_COEF_B1_0_ADDRESS
#define BB_TXIQCORR_RXPATH_COEF_B1_0_HW_MASK                         0x0003ffff
#define BB_TXIQCORR_RXPATH_COEF_B1_0_SW_MASK                         0x0003ffff
#define BB_TXIQCORR_RXPATH_COEF_B1_0_HW_WRITE_MASK                   0x00000000
#define BB_TXIQCORR_RXPATH_COEF_B1_0_SW_WRITE_MASK                   0x0003ffff
#define BB_TXIQCORR_RXPATH_COEF_B1_0_RSTMASK                         0xffffffff
#define BB_TXIQCORR_RXPATH_COEF_B1_0_RESET                           0x00000000

// Skip 8d4 (BB_TXIQCORR_RXPATH_COEF_B1_1) - 90c (BB_TXIQCORR_RXPATH_COEF_B1_15) for brevity
// 0x0910 (BB_RXIQCORR_RXPATH_COEF_B1_0)
#define BB_RXIQCORR_RXPATH_COEF_B1_0_RXIQCORR_RXPATH_COEF_CHN1_MSB   17
#define BB_RXIQCORR_RXPATH_COEF_B1_0_RXIQCORR_RXPATH_COEF_CHN1_LSB   0
#define BB_RXIQCORR_RXPATH_COEF_B1_0_RXIQCORR_RXPATH_COEF_CHN1_MASK  0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_B1_0_RXIQCORR_RXPATH_COEF_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_B1_0_RXIQCORR_RXPATH_COEF_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_B1_0_RXIQCORR_RXPATH_COEF_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_B1_0_RXIQCORR_RXPATH_COEF_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_B1_0_RXIQCORR_RXPATH_COEF_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_B1_0_RXIQCORR_RXPATH_COEF_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_B1_0_RXIQCORR_RXPATH_COEF_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_B1_0_ADDRESS                         0x0910
#define BB_RXIQCORR_RXPATH_COEF_B1_ADDRESS                           BB_RXIQCORR_RXPATH_COEF_B1_0_ADDRESS
#define BB_RXIQCORR_RXPATH_COEF_B1_0_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_B1_0_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_B1_0_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_RXPATH_COEF_B1_0_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_B1_0_RSTMASK                         0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_B1_0_RESET                           0x00000000

// Skip 914 (BB_RXIQCORR_RXPATH_COEF_B1_1) - 94c (BB_RXIQCORR_RXPATH_COEF_B1_15) for brevity
// 0x0950 (BB_RXIQCORR_TXPATH_COEF_B1_0)
#define BB_RXIQCORR_TXPATH_COEF_B1_0_RXIQCORR_TXPATH_COEF_CHN1_MSB   17
#define BB_RXIQCORR_TXPATH_COEF_B1_0_RXIQCORR_TXPATH_COEF_CHN1_LSB   0
#define BB_RXIQCORR_TXPATH_COEF_B1_0_RXIQCORR_TXPATH_COEF_CHN1_MASK  0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_B1_0_RXIQCORR_TXPATH_COEF_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_B1_0_RXIQCORR_TXPATH_COEF_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_B1_0_RXIQCORR_TXPATH_COEF_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_B1_0_RXIQCORR_TXPATH_COEF_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_B1_0_RXIQCORR_TXPATH_COEF_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_B1_0_RXIQCORR_TXPATH_COEF_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_B1_0_RXIQCORR_TXPATH_COEF_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_B1_0_ADDRESS                         0x0950
#define BB_RXIQCORR_TXPATH_COEF_B1_ADDRESS                           BB_RXIQCORR_TXPATH_COEF_B1_0_ADDRESS
#define BB_RXIQCORR_TXPATH_COEF_B1_0_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_B1_0_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_B1_0_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_TXPATH_COEF_B1_0_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_B1_0_RSTMASK                         0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_B1_0_RESET                           0x00000000

// Skip 954 (BB_RXIQCORR_TXPATH_COEF_B1_1) - 98c (BB_RXIQCORR_TXPATH_COEF_B1_15) for brevity
// 0x0a40 (BB_RXCAL_TX_IQCORR_IDX_7_0_B1)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_MSB 31
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_LSB 28
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_MASK 0xf0000000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_MSB 27
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_LSB 24
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_MASK 0x0f000000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_MSB 23
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_LSB 20
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_MASK 0x00f00000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_MSB 19
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_LSB 16
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_MASK 0x000f0000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_MSB 15
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_LSB 12
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_MASK 0x0000f000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_MSB 11
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_LSB 8
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_MASK 0x00000f00
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_MSB 7
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_LSB 4
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_MASK 0x000000f0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_MSB 3
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_LSB 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_MASK 0x0000000f
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_ADDRESS                        0x0a40
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_HW_MASK                        0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_SW_MASK                        0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_SW_WRITE_MASK                  0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RSTMASK                        0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RESET                          0x00000000

// 0x0a44 (BB_RXCAL_TX_IQCORR_IDX_15_8_B1)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_MSB 31
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_LSB 28
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_MASK 0xf0000000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_MSB 27
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_LSB 24
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_MASK 0x0f000000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_MSB 23
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_LSB 20
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_MASK 0x00f00000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_MSB 19
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_LSB 16
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_MASK 0x000f0000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_MSB 15
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_LSB 12
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_MASK 0x0000f000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_MSB 11
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_LSB 8
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_MASK 0x00000f00
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_MSB 7
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_LSB 4
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_MASK 0x000000f0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_MSB 3
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_LSB 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_MASK 0x0000000f
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_ADDRESS                       0x0a44
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_HW_MASK                       0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_SW_MASK                       0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_HW_WRITE_MASK                 0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_SW_WRITE_MASK                 0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RSTMASK                       0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RESET                         0x00000000

// 0x0a48 (BB_RXCAL_TX_IQCORR_IDX_23_16_B1)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_MSB 31
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_LSB 28
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_MASK 0xf0000000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_MSB 27
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_LSB 24
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_MASK 0x0f000000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_MSB 23
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_LSB 20
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_MASK 0x00f00000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_MSB 19
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_LSB 16
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_MASK 0x000f0000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_MSB 15
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_LSB 12
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_MASK 0x0000f000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_MSB 11
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_LSB 8
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_MASK 0x00000f00
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_MSB 7
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_LSB 4
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_MASK 0x000000f0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_MSB 3
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_LSB 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_MASK 0x0000000f
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_ADDRESS                      0x0a48
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_HW_MASK                      0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_SW_MASK                      0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_HW_WRITE_MASK                0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_SW_WRITE_MASK                0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RSTMASK                      0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RESET                        0x00000000

// 0x0a4c (BB_RXCAL_TX_IQCORR_IDX_31_24_B1)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_MSB 31
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_LSB 28
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_MASK 0xf0000000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_MSB 27
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_LSB 24
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_MASK 0x0f000000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_MSB 23
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_LSB 20
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_MASK 0x00f00000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_MSB 19
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_LSB 16
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_MASK 0x000f0000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_MSB 15
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_LSB 12
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_MASK 0x0000f000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_MSB 11
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_LSB 8
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_MASK 0x00000f00
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_MSB 7
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_LSB 4
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_MASK 0x000000f0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_MSB 3
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_LSB 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_MASK 0x0000000f
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_ADDRESS                      0x0a4c
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_HW_MASK                      0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_SW_MASK                      0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_HW_WRITE_MASK                0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_SW_WRITE_MASK                0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RSTMASK                      0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RESET                        0x00000000

// 0x0a50 (BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_2_MSB    29
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_2_LSB    20
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_2_MASK   0x3ff00000
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_2_GET(x) (((x) & BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_2_MASK) >> BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_2_LSB)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_2_SET(x) (((0 | (x)) << BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_2_LSB) & BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_2_MASK)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_2_RESET  0
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_1_MSB    19
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_1_LSB    10
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_1_MASK   0x000ffc00
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_1_GET(x) (((x) & BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_1_MASK) >> BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_1_LSB)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_1_SET(x) (((0 | (x)) << BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_1_LSB) & BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_1_MASK)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_1_RESET  0
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_0_MSB    9
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_0_LSB    0
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_0_MASK   0x000003ff
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_0_GET(x) (((x) & BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_0_MASK) >> BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_0_LSB)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_0_SET(x) (((0 | (x)) << BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_0_LSB) & BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_0_MASK)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_PAPRD_SM_SIG_GAIN_0_RESET  0
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_ADDRESS                    0x0a50
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_HW_MASK                    0x3fffffff
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_SW_MASK                    0x3fffffff
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_HW_WRITE_MASK              0x00000000
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_SW_WRITE_MASK              0x3fffffff
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_RSTMASK                    0xc0000000
#define BB_PAPRD_SM_SIG_GAIN_TABLE_0_2_B1_RESET                      0x00000000

// 0x0a54 (BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_5_MSB    29
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_5_LSB    20
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_5_MASK   0x3ff00000
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_5_GET(x) (((x) & BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_5_MASK) >> BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_5_LSB)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_5_SET(x) (((0 | (x)) << BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_5_LSB) & BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_5_MASK)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_5_RESET  0
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_4_MSB    19
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_4_LSB    10
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_4_MASK   0x000ffc00
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_4_GET(x) (((x) & BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_4_MASK) >> BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_4_LSB)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_4_SET(x) (((0 | (x)) << BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_4_LSB) & BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_4_MASK)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_4_RESET  0
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_3_MSB    9
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_3_LSB    0
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_3_MASK   0x000003ff
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_3_GET(x) (((x) & BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_3_MASK) >> BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_3_LSB)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_3_SET(x) (((0 | (x)) << BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_3_LSB) & BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_3_MASK)
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_PAPRD_SM_SIG_GAIN_3_RESET  0
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_ADDRESS                    0x0a54
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_HW_MASK                    0x3fffffff
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_SW_MASK                    0x3fffffff
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_HW_WRITE_MASK              0x00000000
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_SW_WRITE_MASK              0x3fffffff
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_RSTMASK                    0xc0000000
#define BB_PAPRD_SM_SIG_GAIN_TABLE_3_5_B1_RESET                      0x00000000

// 0x0a70 (BB_PREEMP_COEF_2G_SET0_B1)
#define BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_Q_0_B1_MSB       23
#define BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_Q_0_B1_LSB       12
#define BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_Q_0_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_Q_0_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_Q_0_B1_MASK) >> BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_Q_0_B1_LSB)
#define BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_Q_0_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_Q_0_B1_LSB) & BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_Q_0_B1_MASK)
#define BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_Q_0_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_I_0_B1_MSB       11
#define BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_I_0_B1_LSB       0
#define BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_I_0_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_I_0_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_I_0_B1_MASK) >> BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_I_0_B1_LSB)
#define BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_I_0_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_I_0_B1_LSB) & BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_I_0_B1_MASK)
#define BB_PREEMP_COEF_2G_SET0_B1_TX_PREEMP_COEF_2G_I_0_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET0_B1_ADDRESS                            0x0a70
#define BB_PREEMP_COEF_2G_SET0_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET0_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET0_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET0_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET0_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET0_B1_RESET                              0x00000000

// 0x0a74 (BB_PREEMP_COEF_2G_SET1_B1)
#define BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_Q_1_B1_MSB       23
#define BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_Q_1_B1_LSB       12
#define BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_Q_1_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_Q_1_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_Q_1_B1_MASK) >> BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_Q_1_B1_LSB)
#define BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_Q_1_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_Q_1_B1_LSB) & BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_Q_1_B1_MASK)
#define BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_Q_1_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_I_1_B1_MSB       11
#define BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_I_1_B1_LSB       0
#define BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_I_1_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_I_1_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_I_1_B1_MASK) >> BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_I_1_B1_LSB)
#define BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_I_1_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_I_1_B1_LSB) & BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_I_1_B1_MASK)
#define BB_PREEMP_COEF_2G_SET1_B1_TX_PREEMP_COEF_2G_I_1_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET1_B1_ADDRESS                            0x0a74
#define BB_PREEMP_COEF_2G_SET1_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET1_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET1_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET1_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET1_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET1_B1_RESET                              0x00000000

// 0x0a78 (BB_PREEMP_COEF_2G_SET2_B1)
#define BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_Q_2_B1_MSB       23
#define BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_Q_2_B1_LSB       12
#define BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_Q_2_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_Q_2_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_Q_2_B1_MASK) >> BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_Q_2_B1_LSB)
#define BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_Q_2_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_Q_2_B1_LSB) & BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_Q_2_B1_MASK)
#define BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_Q_2_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_I_2_B1_MSB       11
#define BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_I_2_B1_LSB       0
#define BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_I_2_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_I_2_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_I_2_B1_MASK) >> BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_I_2_B1_LSB)
#define BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_I_2_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_I_2_B1_LSB) & BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_I_2_B1_MASK)
#define BB_PREEMP_COEF_2G_SET2_B1_TX_PREEMP_COEF_2G_I_2_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET2_B1_ADDRESS                            0x0a78
#define BB_PREEMP_COEF_2G_SET2_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET2_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET2_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET2_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET2_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET2_B1_RESET                              0x00000000

// 0x0a7c (BB_PREEMP_COEF_2G_SET3_B1)
#define BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_Q_3_B1_MSB       23
#define BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_Q_3_B1_LSB       12
#define BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_Q_3_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_Q_3_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_Q_3_B1_MASK) >> BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_Q_3_B1_LSB)
#define BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_Q_3_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_Q_3_B1_LSB) & BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_Q_3_B1_MASK)
#define BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_Q_3_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_I_3_B1_MSB       11
#define BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_I_3_B1_LSB       0
#define BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_I_3_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_I_3_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_I_3_B1_MASK) >> BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_I_3_B1_LSB)
#define BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_I_3_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_I_3_B1_LSB) & BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_I_3_B1_MASK)
#define BB_PREEMP_COEF_2G_SET3_B1_TX_PREEMP_COEF_2G_I_3_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET3_B1_ADDRESS                            0x0a7c
#define BB_PREEMP_COEF_2G_SET3_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET3_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET3_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET3_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET3_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET3_B1_RESET                              0x00000000

// 0x0a80 (BB_PREEMP_COEF_2G_SET4_B1)
#define BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_Q_4_B1_MSB       23
#define BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_Q_4_B1_LSB       12
#define BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_Q_4_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_Q_4_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_Q_4_B1_MASK) >> BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_Q_4_B1_LSB)
#define BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_Q_4_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_Q_4_B1_LSB) & BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_Q_4_B1_MASK)
#define BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_Q_4_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_I_4_B1_MSB       11
#define BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_I_4_B1_LSB       0
#define BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_I_4_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_I_4_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_I_4_B1_MASK) >> BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_I_4_B1_LSB)
#define BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_I_4_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_I_4_B1_LSB) & BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_I_4_B1_MASK)
#define BB_PREEMP_COEF_2G_SET4_B1_TX_PREEMP_COEF_2G_I_4_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET4_B1_ADDRESS                            0x0a80
#define BB_PREEMP_COEF_2G_SET4_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET4_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET4_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET4_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET4_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET4_B1_RESET                              0x00000000

// 0x0a84 (BB_PREEMP_COEF_2G_SET5_B1)
#define BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_Q_5_B1_MSB       23
#define BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_Q_5_B1_LSB       12
#define BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_Q_5_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_Q_5_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_Q_5_B1_MASK) >> BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_Q_5_B1_LSB)
#define BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_Q_5_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_Q_5_B1_LSB) & BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_Q_5_B1_MASK)
#define BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_Q_5_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_I_5_B1_MSB       11
#define BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_I_5_B1_LSB       0
#define BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_I_5_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_I_5_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_I_5_B1_MASK) >> BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_I_5_B1_LSB)
#define BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_I_5_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_I_5_B1_LSB) & BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_I_5_B1_MASK)
#define BB_PREEMP_COEF_2G_SET5_B1_TX_PREEMP_COEF_2G_I_5_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET5_B1_ADDRESS                            0x0a84
#define BB_PREEMP_COEF_2G_SET5_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET5_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET5_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET5_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET5_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET5_B1_RESET                              0x00000000

// 0x0a88 (BB_PREEMP_COEF_2G_SET6_B1)
#define BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_Q_6_B1_MSB       23
#define BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_Q_6_B1_LSB       12
#define BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_Q_6_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_Q_6_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_Q_6_B1_MASK) >> BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_Q_6_B1_LSB)
#define BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_Q_6_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_Q_6_B1_LSB) & BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_Q_6_B1_MASK)
#define BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_Q_6_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_I_6_B1_MSB       11
#define BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_I_6_B1_LSB       0
#define BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_I_6_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_I_6_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_I_6_B1_MASK) >> BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_I_6_B1_LSB)
#define BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_I_6_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_I_6_B1_LSB) & BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_I_6_B1_MASK)
#define BB_PREEMP_COEF_2G_SET6_B1_TX_PREEMP_COEF_2G_I_6_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET6_B1_ADDRESS                            0x0a88
#define BB_PREEMP_COEF_2G_SET6_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET6_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET6_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET6_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET6_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET6_B1_RESET                              0x00000000

// 0x0a8c (BB_PREEMP_COEF_2G_SET7_B1)
#define BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_Q_7_B1_MSB       23
#define BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_Q_7_B1_LSB       12
#define BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_Q_7_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_Q_7_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_Q_7_B1_MASK) >> BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_Q_7_B1_LSB)
#define BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_Q_7_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_Q_7_B1_LSB) & BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_Q_7_B1_MASK)
#define BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_Q_7_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_I_7_B1_MSB       11
#define BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_I_7_B1_LSB       0
#define BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_I_7_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_I_7_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_I_7_B1_MASK) >> BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_I_7_B1_LSB)
#define BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_I_7_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_I_7_B1_LSB) & BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_I_7_B1_MASK)
#define BB_PREEMP_COEF_2G_SET7_B1_TX_PREEMP_COEF_2G_I_7_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET7_B1_ADDRESS                            0x0a8c
#define BB_PREEMP_COEF_2G_SET7_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET7_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET7_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET7_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET7_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET7_B1_RESET                              0x00000000

// 0x0a90 (BB_PREEMP_COEF_2G_SET8_B1)
#define BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_Q_8_B1_MSB       23
#define BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_Q_8_B1_LSB       12
#define BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_Q_8_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_Q_8_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_Q_8_B1_MASK) >> BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_Q_8_B1_LSB)
#define BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_Q_8_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_Q_8_B1_LSB) & BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_Q_8_B1_MASK)
#define BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_Q_8_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_I_8_B1_MSB       11
#define BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_I_8_B1_LSB       0
#define BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_I_8_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_I_8_B1_GET(x)    (((x) & BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_I_8_B1_MASK) >> BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_I_8_B1_LSB)
#define BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_I_8_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_I_8_B1_LSB) & BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_I_8_B1_MASK)
#define BB_PREEMP_COEF_2G_SET8_B1_TX_PREEMP_COEF_2G_I_8_B1_RESET     0
#define BB_PREEMP_COEF_2G_SET8_B1_ADDRESS                            0x0a90
#define BB_PREEMP_COEF_2G_SET8_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET8_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_2G_SET8_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_2G_SET8_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_2G_SET8_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_2G_SET8_B1_RESET                              0x00000000

// 0x0a94 (BB_PREEMP_COEF_5G_SET0_B1)
#define BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_Q_0_B1_MSB       23
#define BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_Q_0_B1_LSB       12
#define BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_Q_0_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_Q_0_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_Q_0_B1_MASK) >> BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_Q_0_B1_LSB)
#define BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_Q_0_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_Q_0_B1_LSB) & BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_Q_0_B1_MASK)
#define BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_Q_0_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_I_0_B1_MSB       11
#define BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_I_0_B1_LSB       0
#define BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_I_0_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_I_0_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_I_0_B1_MASK) >> BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_I_0_B1_LSB)
#define BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_I_0_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_I_0_B1_LSB) & BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_I_0_B1_MASK)
#define BB_PREEMP_COEF_5G_SET0_B1_TX_PREEMP_COEF_5G_I_0_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET0_B1_ADDRESS                            0x0a94
#define BB_PREEMP_COEF_5G_SET0_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET0_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET0_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET0_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET0_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET0_B1_RESET                              0x00000000

// 0x0a98 (BB_PREEMP_COEF_5G_SET1_B1)
#define BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_Q_1_B1_MSB       23
#define BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_Q_1_B1_LSB       12
#define BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_Q_1_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_Q_1_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_Q_1_B1_MASK) >> BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_Q_1_B1_LSB)
#define BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_Q_1_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_Q_1_B1_LSB) & BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_Q_1_B1_MASK)
#define BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_Q_1_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_I_1_B1_MSB       11
#define BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_I_1_B1_LSB       0
#define BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_I_1_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_I_1_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_I_1_B1_MASK) >> BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_I_1_B1_LSB)
#define BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_I_1_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_I_1_B1_LSB) & BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_I_1_B1_MASK)
#define BB_PREEMP_COEF_5G_SET1_B1_TX_PREEMP_COEF_5G_I_1_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET1_B1_ADDRESS                            0x0a98
#define BB_PREEMP_COEF_5G_SET1_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET1_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET1_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET1_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET1_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET1_B1_RESET                              0x00000000

// 0x0a9c (BB_PREEMP_COEF_5G_SET2_B1)
#define BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_Q_2_B1_MSB       23
#define BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_Q_2_B1_LSB       12
#define BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_Q_2_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_Q_2_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_Q_2_B1_MASK) >> BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_Q_2_B1_LSB)
#define BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_Q_2_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_Q_2_B1_LSB) & BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_Q_2_B1_MASK)
#define BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_Q_2_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_I_2_B1_MSB       11
#define BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_I_2_B1_LSB       0
#define BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_I_2_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_I_2_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_I_2_B1_MASK) >> BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_I_2_B1_LSB)
#define BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_I_2_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_I_2_B1_LSB) & BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_I_2_B1_MASK)
#define BB_PREEMP_COEF_5G_SET2_B1_TX_PREEMP_COEF_5G_I_2_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET2_B1_ADDRESS                            0x0a9c
#define BB_PREEMP_COEF_5G_SET2_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET2_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET2_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET2_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET2_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET2_B1_RESET                              0x00000000

// 0x0aa0 (BB_PREEMP_COEF_5G_SET3_B1)
#define BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_Q_3_B1_MSB       23
#define BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_Q_3_B1_LSB       12
#define BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_Q_3_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_Q_3_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_Q_3_B1_MASK) >> BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_Q_3_B1_LSB)
#define BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_Q_3_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_Q_3_B1_LSB) & BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_Q_3_B1_MASK)
#define BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_Q_3_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_I_3_B1_MSB       11
#define BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_I_3_B1_LSB       0
#define BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_I_3_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_I_3_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_I_3_B1_MASK) >> BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_I_3_B1_LSB)
#define BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_I_3_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_I_3_B1_LSB) & BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_I_3_B1_MASK)
#define BB_PREEMP_COEF_5G_SET3_B1_TX_PREEMP_COEF_5G_I_3_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET3_B1_ADDRESS                            0x0aa0
#define BB_PREEMP_COEF_5G_SET3_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET3_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET3_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET3_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET3_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET3_B1_RESET                              0x00000000

// 0x0aa4 (BB_PREEMP_COEF_5G_SET4_B1)
#define BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_Q_4_B1_MSB       23
#define BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_Q_4_B1_LSB       12
#define BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_Q_4_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_Q_4_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_Q_4_B1_MASK) >> BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_Q_4_B1_LSB)
#define BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_Q_4_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_Q_4_B1_LSB) & BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_Q_4_B1_MASK)
#define BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_Q_4_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_I_4_B1_MSB       11
#define BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_I_4_B1_LSB       0
#define BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_I_4_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_I_4_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_I_4_B1_MASK) >> BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_I_4_B1_LSB)
#define BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_I_4_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_I_4_B1_LSB) & BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_I_4_B1_MASK)
#define BB_PREEMP_COEF_5G_SET4_B1_TX_PREEMP_COEF_5G_I_4_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET4_B1_ADDRESS                            0x0aa4
#define BB_PREEMP_COEF_5G_SET4_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET4_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET4_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET4_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET4_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET4_B1_RESET                              0x00000000

// 0x0aa8 (BB_PREEMP_COEF_5G_SET5_B1)
#define BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_Q_5_B1_MSB       23
#define BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_Q_5_B1_LSB       12
#define BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_Q_5_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_Q_5_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_Q_5_B1_MASK) >> BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_Q_5_B1_LSB)
#define BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_Q_5_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_Q_5_B1_LSB) & BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_Q_5_B1_MASK)
#define BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_Q_5_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_I_5_B1_MSB       11
#define BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_I_5_B1_LSB       0
#define BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_I_5_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_I_5_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_I_5_B1_MASK) >> BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_I_5_B1_LSB)
#define BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_I_5_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_I_5_B1_LSB) & BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_I_5_B1_MASK)
#define BB_PREEMP_COEF_5G_SET5_B1_TX_PREEMP_COEF_5G_I_5_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET5_B1_ADDRESS                            0x0aa8
#define BB_PREEMP_COEF_5G_SET5_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET5_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET5_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET5_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET5_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET5_B1_RESET                              0x00000000

// 0x0aac (BB_PREEMP_COEF_5G_SET6_B1)
#define BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_Q_6_B1_MSB       23
#define BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_Q_6_B1_LSB       12
#define BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_Q_6_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_Q_6_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_Q_6_B1_MASK) >> BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_Q_6_B1_LSB)
#define BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_Q_6_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_Q_6_B1_LSB) & BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_Q_6_B1_MASK)
#define BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_Q_6_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_I_6_B1_MSB       11
#define BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_I_6_B1_LSB       0
#define BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_I_6_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_I_6_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_I_6_B1_MASK) >> BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_I_6_B1_LSB)
#define BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_I_6_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_I_6_B1_LSB) & BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_I_6_B1_MASK)
#define BB_PREEMP_COEF_5G_SET6_B1_TX_PREEMP_COEF_5G_I_6_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET6_B1_ADDRESS                            0x0aac
#define BB_PREEMP_COEF_5G_SET6_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET6_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET6_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET6_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET6_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET6_B1_RESET                              0x00000000

// 0x0ab0 (BB_PREEMP_COEF_5G_SET7_B1)
#define BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_Q_7_B1_MSB       23
#define BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_Q_7_B1_LSB       12
#define BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_Q_7_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_Q_7_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_Q_7_B1_MASK) >> BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_Q_7_B1_LSB)
#define BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_Q_7_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_Q_7_B1_LSB) & BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_Q_7_B1_MASK)
#define BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_Q_7_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_I_7_B1_MSB       11
#define BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_I_7_B1_LSB       0
#define BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_I_7_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_I_7_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_I_7_B1_MASK) >> BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_I_7_B1_LSB)
#define BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_I_7_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_I_7_B1_LSB) & BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_I_7_B1_MASK)
#define BB_PREEMP_COEF_5G_SET7_B1_TX_PREEMP_COEF_5G_I_7_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET7_B1_ADDRESS                            0x0ab0
#define BB_PREEMP_COEF_5G_SET7_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET7_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET7_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET7_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET7_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET7_B1_RESET                              0x00000000

// 0x0ab4 (BB_PREEMP_COEF_5G_SET8_B1)
#define BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_Q_8_B1_MSB       23
#define BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_Q_8_B1_LSB       12
#define BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_Q_8_B1_MASK      0x00fff000
#define BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_Q_8_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_Q_8_B1_MASK) >> BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_Q_8_B1_LSB)
#define BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_Q_8_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_Q_8_B1_LSB) & BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_Q_8_B1_MASK)
#define BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_Q_8_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_I_8_B1_MSB       11
#define BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_I_8_B1_LSB       0
#define BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_I_8_B1_MASK      0x00000fff
#define BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_I_8_B1_GET(x)    (((x) & BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_I_8_B1_MASK) >> BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_I_8_B1_LSB)
#define BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_I_8_B1_SET(x)    (((0 | (x)) << BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_I_8_B1_LSB) & BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_I_8_B1_MASK)
#define BB_PREEMP_COEF_5G_SET8_B1_TX_PREEMP_COEF_5G_I_8_B1_RESET     0
#define BB_PREEMP_COEF_5G_SET8_B1_ADDRESS                            0x0ab4
#define BB_PREEMP_COEF_5G_SET8_B1_HW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET8_B1_SW_MASK                            0x00ffffff
#define BB_PREEMP_COEF_5G_SET8_B1_HW_WRITE_MASK                      0x00000000
#define BB_PREEMP_COEF_5G_SET8_B1_SW_WRITE_MASK                      0x00ffffff
#define BB_PREEMP_COEF_5G_SET8_B1_RSTMASK                            0xffffffff
#define BB_PREEMP_COEF_5G_SET8_B1_RESET                              0x00000000

// 0x0b00 (BB_TX_PLYBCK_CTRL_0_B1)
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_NSAMPLES_MSB                31
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_NSAMPLES_LSB                16
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_NSAMPLES_MASK               0xffff0000
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_NSAMPLES_GET(x)             (((x) & BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_NSAMPLES_MASK) >> BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_NSAMPLES_LSB)
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_NSAMPLES_SET(x)             (((0 | (x)) << BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_NSAMPLES_LSB) & BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_NSAMPLES_MASK)
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_NSAMPLES_RESET              0
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_START_ADDR_MSB              15
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_START_ADDR_LSB              8
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_START_ADDR_MASK             0x0000ff00
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_START_ADDR_GET(x)           (((x) & BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_START_ADDR_MASK) >> BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_START_ADDR_LSB)
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_START_ADDR_SET(x)           (((0 | (x)) << BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_START_ADDR_LSB) & BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_START_ADDR_MASK)
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_START_ADDR_RESET            0
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_DPD_TRAIN_MSB               4
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_DPD_TRAIN_LSB               4
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_DPD_TRAIN_MASK              0x00000010
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_DPD_TRAIN_GET(x)            (((x) & BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_DPD_TRAIN_MASK) >> BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_DPD_TRAIN_LSB)
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_DPD_TRAIN_SET(x)            (((0 | (x)) << BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_DPD_TRAIN_LSB) & BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_DPD_TRAIN_MASK)
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_DPD_TRAIN_RESET             0
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_RD_MODE_MSB                 3
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_RD_MODE_LSB                 2
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_RD_MODE_MASK                0x0000000c
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_RD_MODE_GET(x)              (((x) & BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_RD_MODE_MASK) >> BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_RD_MODE_LSB)
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_RD_MODE_SET(x)              (((0 | (x)) << BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_RD_MODE_LSB) & BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_RD_MODE_MASK)
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_RD_MODE_RESET               0
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_S2_WRITE_MSB                1
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_S2_WRITE_LSB                1
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_S2_WRITE_MASK               0x00000002
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_S2_WRITE_GET(x)             (((x) & BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_S2_WRITE_MASK) >> BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_S2_WRITE_LSB)
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_S2_WRITE_SET(x)             (((0 | (x)) << BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_S2_WRITE_LSB) & BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_S2_WRITE_MASK)
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_S2_WRITE_RESET              0
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_ENABLE_MSB                  0
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_ENABLE_LSB                  0
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_ENABLE_MASK                 0x00000001
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_ENABLE_GET(x)               (((x) & BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_ENABLE_MASK) >> BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_ENABLE_LSB)
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_ENABLE_SET(x)               (((0 | (x)) << BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_ENABLE_LSB) & BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_ENABLE_MASK)
#define BB_TX_PLYBCK_CTRL_0_B1_TX_PLYBCK_ENABLE_RESET                0
#define BB_TX_PLYBCK_CTRL_0_B1_ADDRESS                               0x0b00
#define BB_TX_PLYBCK_CTRL_0_B1_HW_MASK                               0xffffff1f
#define BB_TX_PLYBCK_CTRL_0_B1_SW_MASK                               0xffffff1f
#define BB_TX_PLYBCK_CTRL_0_B1_HW_WRITE_MASK                         0x00000000
#define BB_TX_PLYBCK_CTRL_0_B1_SW_WRITE_MASK                         0xffffff1f
#define BB_TX_PLYBCK_CTRL_0_B1_RSTMASK                               0x000000e1
#define BB_TX_PLYBCK_CTRL_0_B1_RESET                                 0x00000000

// 0x0c00 (BB_NORMRX_RXIQ_CORR_COEFF_B1_0)
#define BB_NORMRX_RXIQ_CORR_COEFF_B1_0_NORMRX_IQC_COEFF_TABLE_CHN1_MSB 17
#define BB_NORMRX_RXIQ_CORR_COEFF_B1_0_NORMRX_IQC_COEFF_TABLE_CHN1_LSB 0
#define BB_NORMRX_RXIQ_CORR_COEFF_B1_0_NORMRX_IQC_COEFF_TABLE_CHN1_MASK 0x0003ffff
#define BB_NORMRX_RXIQ_CORR_COEFF_B1_0_NORMRX_IQC_COEFF_TABLE_CHN1_GET(x) (((x) & BB_NORMRX_RXIQ_CORR_COEFF_B1_0_NORMRX_IQC_COEFF_TABLE_CHN1_MASK) >> BB_NORMRX_RXIQ_CORR_COEFF_B1_0_NORMRX_IQC_COEFF_TABLE_CHN1_LSB)
#define BB_NORMRX_RXIQ_CORR_COEFF_B1_0_NORMRX_IQC_COEFF_TABLE_CHN1_SET(x) (((0 | (x)) << BB_NORMRX_RXIQ_CORR_COEFF_B1_0_NORMRX_IQC_COEFF_TABLE_CHN1_LSB) & BB_NORMRX_RXIQ_CORR_COEFF_B1_0_NORMRX_IQC_COEFF_TABLE_CHN1_MASK)
#define BB_NORMRX_RXIQ_CORR_COEFF_B1_0_NORMRX_IQC_COEFF_TABLE_CHN1_RESET 0
#define BB_NORMRX_RXIQ_CORR_COEFF_B1_0_ADDRESS                       0x0c00
#define BB_NORMRX_RXIQ_CORR_COEFF_B1_ADDRESS                         BB_NORMRX_RXIQ_CORR_COEFF_B1_0_ADDRESS
#define BB_NORMRX_RXIQ_CORR_COEFF_B1_0_HW_MASK                       0x0003ffff
#define BB_NORMRX_RXIQ_CORR_COEFF_B1_0_SW_MASK                       0x0003ffff
#define BB_NORMRX_RXIQ_CORR_COEFF_B1_0_HW_WRITE_MASK                 0x00000000
#define BB_NORMRX_RXIQ_CORR_COEFF_B1_0_SW_WRITE_MASK                 0x0003ffff
#define BB_NORMRX_RXIQ_CORR_COEFF_B1_0_RSTMASK                       0xffffffff
#define BB_NORMRX_RXIQ_CORR_COEFF_B1_0_RESET                         0x00000000

// Skip c04 (BB_NORMRX_RXIQ_CORR_COEFF_B1_1) - e7c (BB_NORMRX_RXIQ_CORR_COEFF_B1_159) for brevity
// 0x0e80 (BB_PAPRD_MEM_TAB_B1_0)
#define BB_PAPRD_MEM_TAB_B1_0_PAPRD_MEM_MSB                          21
#define BB_PAPRD_MEM_TAB_B1_0_PAPRD_MEM_LSB                          0
#define BB_PAPRD_MEM_TAB_B1_0_PAPRD_MEM_MASK                         0x003fffff
#define BB_PAPRD_MEM_TAB_B1_0_PAPRD_MEM_GET(x)                       (((x) & BB_PAPRD_MEM_TAB_B1_0_PAPRD_MEM_MASK) >> BB_PAPRD_MEM_TAB_B1_0_PAPRD_MEM_LSB)
#define BB_PAPRD_MEM_TAB_B1_0_PAPRD_MEM_SET(x)                       (((0 | (x)) << BB_PAPRD_MEM_TAB_B1_0_PAPRD_MEM_LSB) & BB_PAPRD_MEM_TAB_B1_0_PAPRD_MEM_MASK)
#define BB_PAPRD_MEM_TAB_B1_0_PAPRD_MEM_RESET                        0
#define BB_PAPRD_MEM_TAB_B1_0_ADDRESS                                0x0e80
#define BB_PAPRD_MEM_TAB_B1_ADDRESS                                  BB_PAPRD_MEM_TAB_B1_0_ADDRESS
#define BB_PAPRD_MEM_TAB_B1_0_HW_MASK                                0x003fffff
#define BB_PAPRD_MEM_TAB_B1_0_SW_MASK                                0x003fffff
#define BB_PAPRD_MEM_TAB_B1_0_HW_WRITE_MASK                          0x00000000
#define BB_PAPRD_MEM_TAB_B1_0_SW_WRITE_MASK                          0x003fffff
#define BB_PAPRD_MEM_TAB_B1_0_RSTMASK                                0xffc00000
#define BB_PAPRD_MEM_TAB_B1_0_RESET                                  0x00000000

// Skip e84 (BB_PAPRD_MEM_TAB_B1_1) - 1a7c (BB_PAPRD_MEM_TAB_B1_767) for brevity
// 0x2380 (BB_NORMTX_TXIQ_CORR_COEFF_B1_0)
#define BB_NORMTX_TXIQ_CORR_COEFF_B1_0_NORMTX_IQC_COEFF_TABLE_CHN1_MSB 17
#define BB_NORMTX_TXIQ_CORR_COEFF_B1_0_NORMTX_IQC_COEFF_TABLE_CHN1_LSB 0
#define BB_NORMTX_TXIQ_CORR_COEFF_B1_0_NORMTX_IQC_COEFF_TABLE_CHN1_MASK 0x0003ffff
#define BB_NORMTX_TXIQ_CORR_COEFF_B1_0_NORMTX_IQC_COEFF_TABLE_CHN1_GET(x) (((x) & BB_NORMTX_TXIQ_CORR_COEFF_B1_0_NORMTX_IQC_COEFF_TABLE_CHN1_MASK) >> BB_NORMTX_TXIQ_CORR_COEFF_B1_0_NORMTX_IQC_COEFF_TABLE_CHN1_LSB)
#define BB_NORMTX_TXIQ_CORR_COEFF_B1_0_NORMTX_IQC_COEFF_TABLE_CHN1_SET(x) (((0 | (x)) << BB_NORMTX_TXIQ_CORR_COEFF_B1_0_NORMTX_IQC_COEFF_TABLE_CHN1_LSB) & BB_NORMTX_TXIQ_CORR_COEFF_B1_0_NORMTX_IQC_COEFF_TABLE_CHN1_MASK)
#define BB_NORMTX_TXIQ_CORR_COEFF_B1_0_NORMTX_IQC_COEFF_TABLE_CHN1_RESET 0
#define BB_NORMTX_TXIQ_CORR_COEFF_B1_0_ADDRESS                       0x2380
#define BB_NORMTX_TXIQ_CORR_COEFF_B1_ADDRESS                         BB_NORMTX_TXIQ_CORR_COEFF_B1_0_ADDRESS
#define BB_NORMTX_TXIQ_CORR_COEFF_B1_0_HW_MASK                       0x0003ffff
#define BB_NORMTX_TXIQ_CORR_COEFF_B1_0_SW_MASK                       0x0003ffff
#define BB_NORMTX_TXIQ_CORR_COEFF_B1_0_HW_WRITE_MASK                 0x00000000
#define BB_NORMTX_TXIQ_CORR_COEFF_B1_0_SW_WRITE_MASK                 0x0003ffff
#define BB_NORMTX_TXIQ_CORR_COEFF_B1_0_RSTMASK                       0xffffffff
#define BB_NORMTX_TXIQ_CORR_COEFF_B1_0_RESET                         0x00000000

// Skip 2384 (BB_NORMTX_TXIQ_CORR_COEFF_B1_1) - 25fc (BB_NORMTX_TXIQ_CORR_COEFF_B1_159) for brevity
// 0x3200 (BB_CHANINFO_TAB_B1_0)
#define BB_CHANINFO_TAB_B1_0_CHANINFO_WORD_MSB                       31
#define BB_CHANINFO_TAB_B1_0_CHANINFO_WORD_LSB                       0
#define BB_CHANINFO_TAB_B1_0_CHANINFO_WORD_MASK                      0xffffffff
#define BB_CHANINFO_TAB_B1_0_CHANINFO_WORD_GET(x)                    (((x) & BB_CHANINFO_TAB_B1_0_CHANINFO_WORD_MASK) >> BB_CHANINFO_TAB_B1_0_CHANINFO_WORD_LSB)
#define BB_CHANINFO_TAB_B1_0_CHANINFO_WORD_SET(x)                    (((0 | (x)) << BB_CHANINFO_TAB_B1_0_CHANINFO_WORD_LSB) & BB_CHANINFO_TAB_B1_0_CHANINFO_WORD_MASK)
#define BB_CHANINFO_TAB_B1_0_CHANINFO_WORD_RESET                     0
#define BB_CHANINFO_TAB_B1_0_ADDRESS                                 0x3200
#define BB_CHANINFO_TAB_B1_ADDRESS                                   BB_CHANINFO_TAB_B1_0_ADDRESS
#define BB_CHANINFO_TAB_B1_0_HW_MASK                                 0xffffffff
#define BB_CHANINFO_TAB_B1_0_SW_MASK                                 0xffffffff
#define BB_CHANINFO_TAB_B1_0_HW_WRITE_MASK                           0xffffffff
#define BB_CHANINFO_TAB_B1_0_SW_WRITE_MASK                           0xffffffff
#define BB_CHANINFO_TAB_B1_0_RSTMASK                                 0x00000000
#define BB_CHANINFO_TAB_B1_0_RESET                                   0x00000000

// Skip 3204 (BB_CHANINFO_TAB_B1_1) - 35fc (BB_CHANINFO_TAB_B1_255) for brevity
// 0x8aac (BB_CHN1_TABLES_DUMMY_1)
#define BB_CHN1_TABLES_DUMMY_1_DUMMY1_MSB                            31
#define BB_CHN1_TABLES_DUMMY_1_DUMMY1_LSB                            0
#define BB_CHN1_TABLES_DUMMY_1_DUMMY1_MASK                           0xffffffff
#define BB_CHN1_TABLES_DUMMY_1_DUMMY1_GET(x)                         (((x) & BB_CHN1_TABLES_DUMMY_1_DUMMY1_MASK) >> BB_CHN1_TABLES_DUMMY_1_DUMMY1_LSB)
#define BB_CHN1_TABLES_DUMMY_1_DUMMY1_SET(x)                         (((0 | (x)) << BB_CHN1_TABLES_DUMMY_1_DUMMY1_LSB) & BB_CHN1_TABLES_DUMMY_1_DUMMY1_MASK)
#define BB_CHN1_TABLES_DUMMY_1_DUMMY1_RESET                          0
#define BB_CHN1_TABLES_DUMMY_1_ADDRESS                               0x8aac
#define BB_CHN1_TABLES_DUMMY_1_HW_MASK                               0xffffffff
#define BB_CHN1_TABLES_DUMMY_1_SW_MASK                               0xffffffff
#define BB_CHN1_TABLES_DUMMY_1_HW_WRITE_MASK                         0x00000000
#define BB_CHN1_TABLES_DUMMY_1_SW_WRITE_MASK                         0xffffffff
#define BB_CHN1_TABLES_DUMMY_1_RSTMASK                               0x00000000
#define BB_CHN1_TABLES_DUMMY_1_RESET                                 0x00000000


#endif /* _CHN1_TABLE_MAP_H_ */
